Технически документи
Спецификации
Brand
NexperiaLogic Function
Multifunction
Mounting Type
Surface Mount
Number Of Elements
1
Number of Inputs per Gate
3
Schmitt Trigger Input
No
Package Type
SC-88
Pin Count
6
Logic Family
LVC
Input Type
TTL
Maximum Operating Supply Voltage
5.5 V
Maximum High Level Output Current
-32mA
Maximum Propagation Delay Time @ Maximum CL
10.6 ns @ 50 pF
Minimum Operating Supply Voltage
1.65 V
Maximum Low Level Output Current
32mA
Propagation Delay Test Condition
50pF
Output Type
Single Ended
Length
2.2mm
Height
1mm
Width
1.35mm
Dimensions
2.2 x 1.35 x 1mm
Minimum Operating Temperature
-40 °C
Maximum Operating Temperature
+125 °C
Детайли за продукта
74LVC Family Logic Gates
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
74LVC Family
€ 4,62
€ 0,092 Each (In a Pack of 50) (ex VAT)
Стандарт
50
€ 4,62
€ 0,092 Each (In a Pack of 50) (ex VAT)
Стандарт
50
Информацията за складовите наличности временно не е налична.
Моля, проверете отново по-късно.
количество | Единична цена | Per Опаковка |
---|---|---|
50 - 100 | € 0,092 | € 4,62 |
150 - 250 | € 0,051 | € 2,57 |
300 - 550 | € 0,049 | € 2,45 |
600 - 1150 | € 0,048 | € 2,40 |
1200+ | € 0,047 | € 2,34 |
Технически документи
Спецификации
Brand
NexperiaLogic Function
Multifunction
Mounting Type
Surface Mount
Number Of Elements
1
Number of Inputs per Gate
3
Schmitt Trigger Input
No
Package Type
SC-88
Pin Count
6
Logic Family
LVC
Input Type
TTL
Maximum Operating Supply Voltage
5.5 V
Maximum High Level Output Current
-32mA
Maximum Propagation Delay Time @ Maximum CL
10.6 ns @ 50 pF
Minimum Operating Supply Voltage
1.65 V
Maximum Low Level Output Current
32mA
Propagation Delay Test Condition
50pF
Output Type
Single Ended
Length
2.2mm
Height
1mm
Width
1.35mm
Dimensions
2.2 x 1.35 x 1mm
Minimum Operating Temperature
-40 °C
Maximum Operating Temperature
+125 °C
Детайли за продукта
74LVC Family Logic Gates
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS