Технически документи
Спецификации
Brand
NexperiaLogic Function
Inverter
Input Type
Schmitt Trigger
Number of Elements per Chip
1
Schmitt Trigger Input
Yes
Maximum Propagation Delay Time @ Maximum CL
14 ns @ 50 pF
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Mounting Type
Surface Mount
Package Type
SC-74A
Pin Count
5
Logic Family
LVC
Dimensions
3.1 x 1.7 x 1mm
Maximum Operating Supply Voltage
5.5 V
Height
1mm
Minimum Operating Temperature
-40 °C
Maximum Operating Temperature
+125 °C
Length
3.1mm
Width
1.7mm
Minimum Operating Supply Voltage
1.65 V
Propagation Delay Test Condition
50pF
Детайли за продукта
74LVC Family Inverters & Buffers
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
74LVC Family
Информацията за складовите наличности временно не е налична.
Моля, проверете отново по-късно.
€ 0,133
Each (Supplied on a Reel) (ex VAT)
Производствен пакет (Ролка)
100
€ 0,133
Each (Supplied on a Reel) (ex VAT)
Производствен пакет (Ролка)
100
Купете в насипно състояние
количество | Единична цена | Per Ролка |
---|---|---|
100 - 100 | € 0,133 | € 13,32 |
200 - 400 | € 0,126 | € 12,60 |
500 - 900 | € 0,12 | € 12,01 |
1000 - 1900 | € 0,076 | € 7,61 |
2000+ | € 0,073 | € 7,25 |
Технически документи
Спецификации
Brand
NexperiaLogic Function
Inverter
Input Type
Schmitt Trigger
Number of Elements per Chip
1
Schmitt Trigger Input
Yes
Maximum Propagation Delay Time @ Maximum CL
14 ns @ 50 pF
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Mounting Type
Surface Mount
Package Type
SC-74A
Pin Count
5
Logic Family
LVC
Dimensions
3.1 x 1.7 x 1mm
Maximum Operating Supply Voltage
5.5 V
Height
1mm
Minimum Operating Temperature
-40 °C
Maximum Operating Temperature
+125 °C
Length
3.1mm
Width
1.7mm
Minimum Operating Supply Voltage
1.65 V
Propagation Delay Test Condition
50pF
Детайли за продукта
74LVC Family Inverters & Buffers
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS